3.7.43. Channel routing

A constraint that can be used for modelling channel routing problems. Channel routing consists of creating a layout in a rectangular region of a VLSI chip in order to link together the terminals of different modules of the chip. Connections are usually made by wire segments on two different layers: horizontal wire segments on the first layer are placed along lines called tracks, while vertical wire segments on the second layer connect terminals to the horizontal wire segments, with vias at the intersection.